The present invention relates to a wiring structure of a semiconductor device and a method of fabricating the same, and particularly to a technique of preventing a crack from being generated in an inter-level insulating film under an electrode pad when a connecting member, such as a wire or a bump, is bonded to the electrode pad.
In recent years, in order to allow LSIs to operate at a higher speed, an insulating film having a lower dielectric constant is used as an inter-level insulating film. For this reason, a silicon oxide film containing an organic substance formed by means of an SOG (Spin-On-Glass) method, which will be referred to as an SOG film or layer, has come into use as an inter-level insulating film, in place of an SiO2 film formed by means of a CVD (Chemical Vapor Deposition) method, such as a silicon oxide film formed by using TEOS (tetraethyl orthosilicate), which is referred to as a TEOS film or layer. This is because the SOG film has a dielectric constant lower than that of the TEOS film.
However, the SOG film has a mechanical strength lower than the TEOS film, and has a hardness about one tenth that of the TEOS film. Furthermore, the TEOS film is formed to have a compressive stress. On the other hand, the SOG film has a coefficient of linear expansion higher than that of an Si substrate, and thus the SOG film is formed to have a tensile stress, by means of a present film-formation method with no stress control. Under such circumstances the organic SOG film is apt to easily generate a crack when pressure is applied to the film.
This problem appears most seriously in a step of bonding a connecting member, such as a wire, a bump, or an anisotropic conductivity sheet, to an electrode pad. Specifically, due to pressure applied to the electrode pad during the bonding, a crack is generated in an SOG film directly under the pad. In this respect, FIGS. 10A to 10F are cross-sectional views showing steps of a conventional method of fabricating a wiring structure of a semiconductor device.
First, as shown in FIG. 10A, a wiring layer 2 is formed on an insulating layer 1, and, then, is covered with an organic SOG layer 3. Then, as shown in FIG. 10B, a via hole 4 relative to the wiring layer 2 is formed in the SOG layer 3. Then, Al is deposited over the resultant structure to form an Al film 5 on the SOG layer 3 and in the via hole 4.
Then, as shown in FIG. 10C, the Al film 5 is patterned to form an Al electrode pad 6 by means of lithography and a following RIE (Reactive Ion Etching) method. Then, as shown in FIG. 10D, a passivation layer 7 consisting of, e.g., an organic SOG film, a plasma CVD silicon oxide film, or a plasma CVD silicon nitride film, is formed over the resultant structure.
Then, as shown in FIG. 10E, a through hole 8 is formed in the passivation layer 7 to expose the Al pad 6. Thereafter, dicing and mounting are performed for assembling, and, then, as shown in FIG. 10F, wire bonding is performed relative to the Al pad 6. At this time, a wire 9 is brought into close contact with the Al pad 6 such that pressure is applied to the pad 6, whereby the wire 9 is connected to the pad 6.
In this wire bonding process, a problem arises in that a crack is generated in the SOG layer 3 directly under the pad 6.